Low-Power and Area-Efficient Carry Select Adder. Abstract: Carry Select Adder ( CSLA) is one of the fastest adders used in many data-processing processors to. Low-Power and Area-Efficient Carry Select Adder. P. Sirish Kumar a. S. Kiran b. T . Lakshmana Rao c a: Assistant Professor, Department of Electronics and. Abstract— Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the.
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1. Low-Power and Area-Efficient Carry Select Adder. B. Ramkumar and Harish M Kittur. Abstract—Carry Select Adder (CSLA) is one of the fastest adders used. ABSTRACT: Carry select method has deemed to be a good compromise between cost and performance in carry propagation adder design. However. Request PDF on ResearchGate | Low-power and area-efficient carry select adder using modified BEC-1 converter | Carry Select Adder (CSLA) is one of the.
Group 1. It contains one full adder. Each full adder consists of two XOR gates. Group 2. Group 3. Group 4.
It contains two full adders, one half adder, and one 4-bit BEC. Hence, the reduction in number of switching transistors reduces the power consumption as well as the power-delay product PDP of 8-bit CSLA. Simulation Results The proposed 8-bit CSLA has been successfully tested and synthesized in Tanner Tools using 90 nm technology with a supply voltage of 1.
The power consumption and delay time of proposed 8-bit CSLA are calculated for all input conditions and the worst case power consumption as well as delay time is noted down. The comparison is shown in Table 2. Table 2: Comparison of various carry select adders. Compared with the reversible logic style based 8-bit CSA [ 15 ], the proposed design has The postsimulation input-output waveforms for the 8-bit proposed CSLA are shown in Figures 6 and 7 , respectively.
The proposed design is simulated with a Figure 6: Postsimulation results: a input waveform to. The steps leading to the evaluation are given here.
The delay and area estimation of each group are shown in Fig. And d group5.
H is a Half adder 1 The group2 [see Fig. The sum2 depends on c1 and mux. To further evaluate the performance.
The area indicates the total cell area of the design and the total power is sum of the leakage power. For each word size of the adder. The percentage reduction in the cell area.
The synthesized Verilog netlist and their respective design constraints file SDC are imported to Cadence SoC Encounter and are used to generate automated layout from standard cells and placement and routing . Also plotted is the percentage 16 P a g e. The total power consumed shows a similar trend of increasing reduction in power consumption 7. The delay overhead for the 8. It is clear that the area of the Similarly the area-delay product of the proposed design for The modified CSLA architecture is therefore.
The reduced number of gates of this work offers the great advantage in the reduction of area and also the total power. The power-delay product and also the area-delay product of the proposed design show a decrease for Book edited by A. Flynn and S.. Circuits Syst.
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Schultz and J. IEEE Press.. Application SpecificArray Processors. Upper Saddle River. Ceiang and M. May Srinivas and G. Flag for inappropriate content. Related titles. Low power and area delay efficient carry select adder. Jump to Page. Search inside document. Divakar Umakaran. Bhavani Prasad.
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